The present invention generally relates to semiconductor device manufacturing, and more particularly to a stacked nanowire device having a varying number of nanowire channels.
Due to their superior electrostatics gate-all-around nanowire channel field effect transistors (e.g., nanowire FETs) are expected to enable density scaling beyond current planar CMOS technology. In its basic form, a nanowire FET includes a source, a drain and one or more nanowire channels between the source and the drain. A gate electrode, which wraps around the one or more nanowire channels, regulates electron flow through the nanowire channel between the source and drain.
As the diameter of nanowire channel(s) is reduced to enable better electrostatics, the current carrying surface (or area, in the case of bulk inversion) of each nanowire channel is reduced as well, meaning that more nanowire channels need to be placed in closer proximity to each other to achieve the same density of the current carrying surface or area. For example, nanowire channels with a diameter of 4 nm would need to be placed at a pitch of 12 nm to yield the same effective width as a planar device with the same layout footprint. One way to increase layout density in the width direction is to stack the nanowire channels vertically, rather than using just one layer of them. This is a solution that is unique to gate-all-around devices such as nanowire FETs. Nanowire devices having one or more nanowire channels stacked vertically may be referred to as a stacked nanowire device or a stacked nanowire FET.
A stacked nanowire device may be configured with one or more nanowire channels in one or more layers, each layer having the same number of nanowire channels. For example, a stacked nanowire device may have two layers of six nanowire channels, or a total of twelve nanowire channels. In another example, a stacked nanowire device may have four layers of six nanowire channels, and a total of twenty-four nanowire channels. A stacked nanowire device may alternatively be described as having one or more stacks of nanowire channels (hereinafter “nanowire stack”). In the present example, the number of nanowire stacks corresponds to the number of nanowire channels per layer, as described above. Further, the number of nanowire channels per nanowire stack corresponds to the number of layers, as described above.
The current carrying capacity of a nanowire device may be defined and limited by the total number of nanowire channels in a single device. The total number of nanowire channels in a single device is defined by and limited to the number of layers of nanowire channels and the number of nanowire channels in each layer. In order to design nanowire devices with different or varying current carrying capacities, the total number of nanowire channels may be increased or decreased; however, in devices with more than one nanowire channel per layer, the total number of nanowire channels cannot be increased or decreased by a single nanowire channel. Stated differently, in devices with more than one nanowire channel per layer, the total number of nanowire channels can only be increase or decreased by either, the number of layers, or the number of channels in a nanowire layer. For example, the current carrying capacity of a single nanowire device having a total of twelve nanowire channels, two layers of six nanowire channels, may only be increased or decreased by adding or subtracting either two nanowire channels (e.g. one layer) or by six nanowire channels (e.g. one stack).
Considerable design constraints exist with respect to the current carrying capacity of a single stacked nanowire device. Such constraints limit the design flexibility of such devices with respect to their current carrying capacity.